Verilog Tutorial: begin-end and fork-join :: ElectroSifts.com

module forkjoin(clk, a, b); input clk; output a; output b; reg a, b; initial begin a = 0; b = 0; end always @(posedge clk) fork #2 a = 1; #1 b = 1; join endmodule module forkjoin1(clk, a, b); input clk; output a; output b; reg a, b; initial begin a = 0; b

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