Serial LVDS High-Speed ADC Interface - All Programmable Technologies from Xilinx Inc.

ADC LVDS Interface XAPP524 (v1.1) November 20, 2012 www.xilinx.com 3 The frame clock (FCLK) is a digitized and phase-shifted version of the ADC sample clock. FCLK is phase aligned with the serial data, and all data bits of a sample fit into one frame cloc

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