ASIC-System on Chip-VLSI Design: Verilog code for asynchronous FIFO

Good stuff Murali!! I congratulate your efforts in writing the blog.I wish graduates will find this blog helpful for making their careers in this prospective and ... this is nice..... but is there any verilog code for async fifo using SRAM(dual port SRAM)

asic-soc.blogspot.com